The fabrication of various solid state devices requires the use of planar substrates, or semiconductor wafers, on which integrated circuits are fabricated. The final number, or yield, of functional integrated circuits on a wafer at the end of the IC fabrication process is of utmost importance to semiconductor manufacturers, and increasing the yield of circuits on the wafer is the main goal of semiconductor fabrication. After packaging, the circuits on the wafers are tested, wherein non-functional dies are marked using an inking process and the functional dies on the wafer are separated and sold. IC fabricators increase the yield of dies on a wafer by exploiting economies of scale. Over 1000 dies may be formed on a single wafer which measures from six to twelve inches in diameter.
Various processing steps are used to fabricate integrated circuits on a semiconductor wafer. These steps include sequential deposition of conductive and insulative layers on the silicon wafer substrate; formation of a photoresist or other mask such as titanium oxide or silicon oxide, in the form of the desired metal interconnection pattern, using standard lithographic or photolithographic techniques; subjecting the wafer substrate to a dry etching process to remove material from one or more conducting layers from the areas not covered by the mask, thereby etching the conducting layer or layers in the form of the masked pattern on the substrate; removing or stripping the mask layer from the substrate typically using reactive plasma and chlorine gas, thereby exposing the top surface of the conductive interconnect layer; and cooling and drying the wafer substrate by applying water and nitrogen gas to the wafer substrate.
The numerous processing steps outlined above are used to cumulatively apply multiple electrically conductive and insulative layers on the wafer and pattern the layers to form the circuits. Additional techniques, such as dual damascene processes, are used to form conductive vias which establish electrical contact between vertically-spaced conductive lines or layers in the circuits. The finished semiconductor product includes microelectronic devices including transistors, capacitors and resistors that form the integrated circuits on each of multiple die on a single wafer.
The fabrication of IC devices on a substrate frequently involves electrically isolating adjacent devices on a substrate to prevent short-circuiting of the devices. Shallow trench isolation (STI) is a widely-used technique to isolate adjacent devices fabricated on a substrate. In STI, spaced-apart trench oxides are formed by initially etching trenches in the substrate typically using a dry etching process. A pre-liner oxide film is typically formed on the substrate surfaces in the trenches. A liner oxide layer is then grown on the surfaces of the trenches, typically using thermal processing techniques. The trenches are then filled with CVD oxide and planarized using chemical mechanical planarization (CMP), after which the devices are fabricated. A thin gate oxide on the surface of the substrate extends between the spaced-apart trench oxides.
Silicon oxide (SiO2) is frequently used for its insulating properties as a gate oxide or dielectric in the fabrication of IC devices. As the dimensions of device circuits on substrates become increasingly smaller, the gate dielectric thickness must decrease proportionately in field effect transistors (FETs) to approximately 3 to 3.5 nonometers. Accordingly, device performance and reliability can be adversely affected by such factors as interfacial defects, defect precursors and diffusion of dopants through gate dielectrics, as well as unintended variations in thickness in the gate oxide layer among central and peripheral regions of the layer.
In the semiconductor fabrication industry, minimization of particle contamination on semiconductor wafers increases in importance as the integrated circuit devices on the wafers decrease in size. With the reduced size of the devices, a contaminant having a particular size occupies a relatively larger percentage of the available space for circuit elements on the wafer as compared to wafers containing the larger devices of the past. Moreover, the presence of particles in the integrated circuits compromises the functional integrity of the devices in the finished electronic product. Consequently, after the STI trenches are etched in the substrate and before the liner oxide is deposited in the trenches, the substrate is typically subjected to a cleaning process, such as an RCA cleaning process, to remove particles from the trenches and from the substrate.
The RCA clean process is widely used in the semiconductor industry and includes sequential immersion of substrates in two different chemical baths, commonly known as Standard Clean 1 (SC-1) and Standard Clean 2 (SC-2). The SC-1 bath is an alkaline solution used to remove particles and organic materials from the wafer and includes a mixture of ammonium hydroxide, hydrogen peroxide and DI water. The SC-2 bath is used to remove metals from the surface of the wafer and includes a mixture of hydrochloric acid, hydrogen peroxide and DI water.
Typically, wafers are routed in lots through the STI process. As the cleaning process is carried out to remove particles from the trenches, a pro-liner oxide film for the liner oxide layer is formed on the wafer surface in the trenches by introducing oxygen into the cleaning chamber. Ozone (O3) has been provided in the liquid-state in de-ionized water used to clean the wafers, to facilitate formation of the pro-linor oxide film on the water surface in the trenches. However, this mode of bringing oxygen into contact with the wafer surface has resulted in the formation of pre-liner oxide films of non-uniform thickness.
The wafers are frequently subjected to a “stand-by” or waiting period after placement into the cleaning chamber and prior to commencement of the cleaning and oxide liner formation process. However, because the interior of the cleaning chamber is characterized by relatively low temperatures and low oxygen purity, a low-quality and non-uniform pre-liner oxide film forms on the wafer surface in the trenches. This causes breakdown of the trench oxide subsequently formed on the liner oxide layer in the trenches. Consequently, devices fabricated on the substrate exhibit undesired junction leakage and a narrow device Vt. Accordingly, a new and improved method is needed for forming a pre-liner oxide film on wafer surfaces, particularly in the fabrication of trench oxide structures.
An object of the present invention is to provide a novel method which is suitable for forming an oxide film on a surface.
Another object of the present invention is to provide a novel method which is suitable for forming an oxide film on a surface, particularly a silicon surface, in a variety of applications.
Still another object of the present invention is to provide a novel method which is suitable for forming a pre-liner oxide film on trench surfaces of a substrate in the fabrication of shallow trench isolation (STI) structures.
Yet another object of the present invention is to provide a novel cleaning method which enhances device performance and reliability in the fabrication of semiconductor devices and contributes to GOI (gate oxide integrity) in 300 mm wafer technology.
A still further object of the present invention is to provide a novel cleaning and oxide film-forming method which is characterized by a wide process control window in the fabrication of high aspect ratio STI trenches.
Another object of the present invention is to provide a novel method which enhances uniformity in oxide films on substrates.
Yet another object of the present invention is to provide a novel oxide film forming method which includes providing a substrate in contact with ozone vapor while subjecting the substrate to a cleaning process.
Another object of the present invention is to provide a novel cleaning and oxide film forming method which is characterized by expedited process time, low cost and high process throughput.